1. Field of the Invention
This invention is related to the field of computer systems and, more particularly, to coherence mechanisms in computer systems.
2. Description of the Related Art
Historically, shared memory multiprocessing systems have implemented hardware coherence mechanisms. The hardware coherence mechanisms ensure that updates (stores) to memory locations by one processor (or one process, which may be executed on different processors at different points in time) are consistently observed by all other processors that read (load) the updated memory locations according to a specified ordering model. Implementing coherence may aid the correct and predictable operation of software in a multiprocessing system. While hardware coherence mechanisms simplify the software that executes on the system, the hardware coherence mechanisms may be complex and expensive to implement (especially in terms of design time). Additionally, if errors in the hardware coherence implementation are found, repairing the errors may be costly (if repaired via hardware modification) or limited (if software workarounds are used).
Other systems have used a purely software approach to the issue of shared memory. Generally, the hardware in such systems makes no attempt to ensure that the data for a given memory access (particularly loads) is the most up to date. Software must ensure that non-updated copies of data are invalidated in various caches if coherent memory access is desired. While software mechanisms are more easily repaired if an error is found and are more flexible if changing the coherence scheme is desired, they typically have much lower performance than hardware mechanisms.
One perspective in which software coherence mechanisms particularly suffer is repeated coherence activity involving the same underlying coherence units. Generally, a coherence unit may be any block of data that is treated as a unit for coherence purposes. In many cases, a coherence unit is the same as a cache line, although coherence units may be less than a cache line in size or larger than a cache line in size in various embodiments. Each time coherence activity is needed, the software must get involved to establish the proper state for the desired access to continue. For example, if a coherence unit is first read, software may provide a read-only (e.g. shared or shareable) copy of the coherence unit. If the coherence unit is then written, additional activity may be needed to provide a writeable copy of the same data.